1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FinFET semiconductor devices, and, more specifically, to various novel methods of forming fins with different fin heights.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
In contrast to a planar FET, which, as the name implies, is a generally planar structure, a so-called FinFET device has a three-dimensional (3D) structure. FIG. 1 is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device 10 includes three illustrative fins 14, a gate insulating layer 11, a gate electrode 16, a sidewall spacer 18 and a gate cap 20. A plurality of fin-formation trenches 13 is formed in the substrate 12 to define the fins 14. A recessed layer of insulating material 17 is positioned between the fins 14 and under the gate electrode 16. The overall gate structure is typically comprised of the layer of gate insulating material 11, e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode 16 for the device 10. The fins 14 have a three-dimensional configuration: an exposed height 14H (above the recessed upper surface 17S of the layer of insulating material), a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device 10 when it is operational, i.e., the gate length direction of the device 10. The portions of the fins 14 covered by the gate structure constitute the channel region of the FinFET device 10. The gate structures for such FinFET devices 10 may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques. A FinFET device may have either a tri-gate or dual-gate channel region.
In an integrated circuit device, there are different performance requirements for different functional blocks or regions of the device. It is useful to provide transistors, including FinFET transistors, with different threshold voltages to adapt to the different performance requirements. For example, in some cases, devices may be classified as a regular threshold voltage (RVT) device or a super low threshold voltage (SLVT) device. The actual threshold voltage levels associated with the RVT and SLVT devices may vary depending upon the devices under construction and ongoing advances in device design and manufacturing. In one illustrative example, based upon current-day technologies, an RVT device may be considered to be one having a threshold voltage that falls within the range of about 250-350 mV, such as 300 mV, while an SLVT device may be considered to be a device having a threshold voltage that falls within the range of about 100-200 mV, such as 150 mV. In relative terms, the threshold voltage of the RVT device may be about 150 mV greater than the threshold voltage of the SLVT device.
Generally, threshold voltages may be provided by providing different work function materials in the gate electrode, doping the gate dielectric material or the channel regions of the FinFET device by various implantation processes, etc. However, providing different work function materials in the different regions significantly complicates the process flow. The effectiveness of doping processes can also be affected by the channel length of the transistor devices and the thermal budget. High temperature anneal processes performed to activate implanted dopant material and repair damage to the crystalline structure of the substrate can cause difficulties with diffusion of dopant or stress-inducing ions, stress relaxation and defect generation.
The present disclosure is directed to methods of forming fins with different fin heights that may solve or reduce one or more of the problems identified above.